ASIC Flow

ASIC Flow :

System Specification (idea)

⇓

Architectural Design (data flow)

⇓

Functional Design

⇓

RTL Design and Verification

⇓

Synthesis

⇓

Physical Design

⇓

SignOff (PV, STA, LEC ..)

⇓

Fabrication

⇓

Testing

⇓

Packaging

⇓

Final Chip

VLSI designing is divided into front end and back end. Till synthesis stage, comes under frond end designing. Remaining steps are treated as back end. After synthesis and before physical design, there is DFT team for testing of connectivity of the cells, inserts scan chains etc.., DFT team also tests the chip after fabrication of the chip.

Based on the market survey results, we will finalize our system specifications.

Architectural design : Gives dataflow diagram required to design the chip.

RTL design : Writes the RTL code by using Verilog, VHDL, System Verilog, UVM etc..,

Design Verification : Verifies the consistency of the given RTL code.

Synthesis : converts RTL code into gate level netlist.

Physical Design : Transforms circuit description into physical layout.

SignOff : Various checks are performed at this stage such as

• DRC (Design Rule Check)
• To check whether the design is meeting given physical rules like min pitch, min spacing, min width etc.,
• LVS (Layout Vs Schematic)
• Checking whether connections are properly made by comparing the designed layout by schematic. Throws errors if design has opens, shorts, parameter mismatch etc.,
• LEC (Logic Equivalence Check)
• Formal verification, for checking functionality issues.
• STA (Static Timing Analysis)
• Analyzing timing of the design by checking for violations using the determined calculations.

Fabrication : Manufacturing/creating the IC.
Testing : Tests the fabricated IC.
Tape out : Chip closure