Physical Design Flow

Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed.

The design flow deals with various steps involved such as follows:

Synthesized netlist

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Partitioning

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Sanity checks

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Floorplan

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Power plan

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Placement

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Clock Tree Structure (CTS)

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Routing

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Signoff

Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed.

Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code.

.def is the output file at each step. After routing, the extracted .def file is fed to parasitic extraction tool like StarRC, qRC etc.., that contains its own extraction engine for R and C parasitic extraction. As a result, .spef is generated.

 

It is further given as an input to STA engine (eg: PrimeTime) for timing analysis. If any setup and hold violations are obtained, we have to iterate from routing stage till setup and hold slacks met.

Physical verification (DRC, LVS, ERC) and STA comes under signoff stage. Formal verification is done at every stage for checking the logic equivalence.

Mostly used tools are from

• Synopsys
• Cadence
• Mentor Graphics

Others : Magma.

The cost factors for physical design are Power, Performance and Area.