Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
- Clock Re-convergence Pessimism Removal. Also called as CPPR.
- Let's consider a buffer that is placed in common path
(both data path and clock path).
- Tool calculates max. delays for setup calculation and
min. delays for hold (worst and best case analysis).
- When comes to OCV analysis, tool further considers,
- max. for data path and min. for clock path during
setup analysis.
- max. for clock path and min. for data path during hold
analysis.
- So, buffer placed in common path now has 2 values i.e.,
max. and min. values.
- As we know, a cell can't have two different values at a
particular instant of time. Thereby we calculates the buffer value as,
CRPR = Max. value - min. value
While performing STA,
for setup analysis, CRPR is added in RT whereas in hold analysis, it is
subtracted from RT.
RT + CRPR (for setup)
RT - CRPR (for hold)
Example regarding CRPR
is shown above.
For above figure, CRPR =
1ns - 0.8ns = 0.2ns.
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