Power Dissipation

1. Static Power Dissipation - Due to leakage currents (without any operation) (standby mode)

2. Dynamic Power Dissipation - Due to switching (switching mode)

 

Total power dissipation = Static power diss. + Dynamic power diss.

Static power dissipation is due to:

a) Gate oxide leakage currents

b) Junction leakage currents

c) Sub-threshold currents

Dynamic power dissipation:

a) switching p.d.

b) short circuit p.d.

c) glitching p.d. - large delays

 

Power reduction techniques in CMOS

1. Reduce the supply voltage

2. Using variable clock frequencies and operating voltages.

3. First increase the performance of the circuit (by adding components in parallel) and then reduce the voltage of the circuit. 

*If voltage is reduced before increasing the performance, the delay of the circuit increases.

4. Clock gating and power gating.

 

Dynamic power dissipation can be reduced by reducing:

a) Clock frequency - easy approach but affects the performance majorly.

b) Load capacitance - difficult approach.

c) Rail voltage - done only device technology. It is mostly a standard value and we have very less control over it as this depends on threshold voltage and noise margin.

d) Switching activity parameter - by optimizing algorithms, architecture, logic topology and by using special encoding techniques.

e) Using pipe-lining - operates the internal logic at a lower clock than i/o frequency.

f) Clock gating - avoiding the clock to the unused blocks or components (shutting off the clock).

  

Static power dissipation can be reduced by:

a) power gating - clock gating only reduces the active power consumption but not static power. So, power gating is used.

b) multi-threshold transistor usage - HVT, ULVT, LVT, RVT/SVT.

c) Active back-bias - increasing the bias voltage of the substrate reduces the leakage current as it increases the threshold voltage.