Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
SYNTHESIS
Transformation of idea into manufacturable device to carry out an intended function.
Types of Synthesis :
1. Behavioral Synthesis
- specifications into RTL code.
2. Logical Synthesis
- RTL code to Gate level netlist (.v)
3. Physical Synthesis
- .v to .gdsii (Graphical Data Stream/System Information Interchange)
Completing a round of logical synthesis, Floorplan is done along with rough placement of std. cells. The output of this stage (in the form of .def) is given back to the synthesis tool for better compilation, mostly in terms of area and timing optimization. Its also called Physical Synthesis
Normally, with respect to synopsys tools, Design Compiler is used for logical synthesis and DC Topo is used for Physical Synthesis.
.gdsii contains the 3D view info. of design(& cells) that defines the position of cells along with their connections.
(*Synthesis mostly refers to logical synthesis).
Inputs for synthesis(logical) :
- RTL code
- estimated .sdc (constraints)
- .tf
- libraries
- .upf (Unified Power Format)
- Scan configuration & scan file
- Clock gating information (mostly provided by RTL team)
- Physical Constraints / .def (for physical synthesis using DC Topo)
Stages :
- Translation(T)
- Mapping(M)
- Optimization(O)
Synthesis Flow :
Read RTL
and libraries (T)
⇓
Read UPF
⇓
Link
design
⇓
check_design
⇓
dump
unmapped ddc
⇓
load
constraints
⇓
check_timing
⇓
clock
gating insertion
⇓
scan
insertion
⇓
compile
(synthesis) (M + O)
⇓
dump
mapped ddc
⇓
dump
other outputs (netlist, .scandef, .sdc)
Outputs of this stage are :
- .v (Synthesized Netlist/Gate level netlist) / .ddc (.v + .scandef)
- .sdc
- timing reports
Without any constraints specified, the synthesis tool will generate a non-optimized netlist (which might not satisfy the designers requirements).
Tools used for logical synthesis :
- Design compiler (DC, DCT) - Synopsys
- Fusion compiler (FC) - Synopsys (Synthesis + PnR)
- Genus - cadence (Widely used in cadence tools for synthesis)
- Ambit compiler - Cadence
- RTL compiler - Cadence
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