Placement

It is the process of placing pre-designed cells (std. cells) in a legalized manner such that some objective function is optimized.

Tool takes care of power, timing, congestion etc.., while placement.

Steps of placement :

• Coarse placement
• Legalized placement
• Detailed placement

Coarse placement : placer engine places all the standard cells inside the core area from outside without any legalization.

Legalized placement : places std. cells exactly on the site rows and without any overlaps.

Detailed placement : iterative placement and optimization.

Sanity checks before going to placement stage :

• All macros and ports are to be placed properly and fixed.
• Power routing should be done.
• Preplaced cells should be inserted.
• checking the availability of scan chain information as scan chain reordering is to be done at this stage.

(*Scan chain : logical connectivity of cells in order to form a unified shift register. It is given by DFT team).

place_opt performs scan chain reordering, HFN synthesis along with initial placement and optimization etc..,

> HFN synthesis : nets other than clock that have high fan-out than the required are to be synthesized.

eg : reset, scan enable etc..,

(*Clock is idle in this stage).

> Scan chain reordering : detaching the scan chain and reordered without any change in functionality. It helps in reducing congestion and timing.

Congestion : occurs if required routing resources > available routing resources. It may be due to

• Cell density : more cells in the small area
• Pin density : pins between cells are more than usual/expected.
• Module splitting : cells related to a module/hierarchy gets splitted.
• Bad floorplan : improper macro placement/spacing between them.

Overcomes :

• Modify placement constraints (along with pnet options).
• Partial placement blockage (if due to cell density).
• Reduce placer density level (if due to cell density).
• Cell padding (if due to pin density) - providing proper keepouts/hallos.
• Regions/Bounds (if due to module splitting) (also improves timing)
• Check whether the macros are placed near the boundaries. If not, place them accordingly with proper spacing between them.

If congestion is still a problem, the it is suggested to modify the floorplan.

• Ports are reordered and changed to a metal layer.
• Modify core area size/aspect ratio (if possible). It increases utilization.
• Modify power grid structure.
• Use high metal layers.
• Change width and/or spacing of straps.

Optimization techniques :

• HFN synthesis
• Cell sizing
• Buffering
• Cell swapping/VT swapping
• Logical restructuring
• Bounds
• Magnet placement (improves timing but effects congestion)
• Path groups

Placement methodologies :

• Congestion driven
• Timing driven
• Power driven
• Area driven

Checks to be performed after placement :

• Check legalization
• Power nets should be pre-routed.
• Estimated/acceptable timing
• Estimated/acceptable congestion
• Estimated max. trans/cap (No violations)
• Scan chain should be reordered if have any in the design.
• Qor reports along with timing report
• Utilization and IR check