Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
The Inputs for Physical Design are:
.v or .vg (Synthesized Netlist) :
- It contains logic
interconnection of gates for all cells (std. cells, macros..,).
- Contains list of nets
(*Net : Collection of 2 or more interconnected logic components).
.tf (Technology File) :
- Manufacturing grid
- Physical
characteristics (min. height, min. width, min. area)
- Electrical
characteristics (current density) of layers and vias.
- Colours and Patterns.
- Units and Precisions.
- Physical design rules
like wire-wire spacing, min. width b/w layer and via.
- Stipple patterns.
- Line styles.
- Device
characteristics.
- Coupling capacitances.
- Capacitance models.
- Dielectric values and
thickness.
.sdc (Synopsys Design Constraints) :
- Timing, Design and
Area constraints.
- Operating conditions.
- Logic assignments
- Multi voltage &
power optimization constraints.
- Clock definitions
(creating master clock, generated clock, virtual clock)
- input delay, output
delay and in-out delays.
- Min. and Max. delays.
- Multicycle path and
false path.
(*Clock : used for triggering i.e.,transferring of signal from
source to destination).
.lib (logical LIBrary file) :
- Timing information of
all cells.
- Functionality
information. (for optimization).
- Design rules like
max. transition, max. capacitance and max. fanout.
- Cell delays, setup
time and hold time.
- Wire load models.
- Power information,
PVT conditions, derating factor information.
(*Transition : change of one logic state to
another).
(*Fanout : capability of a logic to drive
multiple similar logics).
.lef (Library/Liberty/Layout Exchange Format) :
- Pin information.
- Height and width,
area (Top view info.).
- Routing directions.
- Pitch.
- Antenna factors.
- Blockage information.
.tlu+ (TLU
plus) :
·
It contains the values of
parasitic resistances(R) and capacitances(C) in order to calculate the net
delay values for PnR.
.def (Design Exchange Format)
:
- Name itself indicates
that the file is used for exchanging the design information.
- contains the
information regarding the position of cells, blockages, ports etc.., along
with die and core information.
Basically, it
contains all the information of the previous stage. We can import the previous
stage design by just sourcing this file rather than copying the complete design.
Eg: .def of
floorplan contains info. about macro placement, port placement, cut rows,
physical cells, pg routing etc..,
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