Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
SANITY CHECKS
We check mainly the following input files:
1. Netlist
2. SDC files
3. Library files
4. Design information
The following commands are used for performing sanity checks and generation of the reports:
- check_design
- check_timing
- check_library
- check_legality
- check_tlu_plus_files
- check_mv_design
- report_constraints
- report_timing
- report_qor
➢check_design : checks the compatibility of the design and checks the potential problems like unloaded input ports and undriven output ports, mismatched pin count, multidriven nets etc.., It also reports unification problems.
➢check_timing : checks for any unconstrained paths as PnR tool optimizes the constrained paths only.
➢check_library : performs the consistency checks within logical and physical libraries. It checks library qualities in
physical library quality logic
(vs)
physical library consistency logic
(vs)
logical library consistency
(vs)
physical library consistency logic
(vs)
logical library consistency
and shows if any cells missing, missing/mismatched pins. In physical library, it checks for any duplicate cell names within the multiple reference libraries.
➢check_legality : checks the legalization of the cells (i.e., the cells should not be overlapped and should be placed in cut rows correctly).
➢check_tlu_plus_files : checks whether the required R and C values are provided (or) not.
➢check_mv_design : checks the design whether its multi voltage design (or) single voltage design and also checks whether pg connections are properly defined or not.
➢report_constraints : checks and reports Worst Negative Slack(WNS), Total Negative Slack(TNS) and Design Rule Constraints(DRC) violations.
➢report_timing : reports timing information of the design like worst setup path.
➢report_qor : reports qor info.(i.e., timing path group and cell count details), statistics of the current design(i.e., combo., non-combo., and total area) and also reports static power, design rule violations and compile time details.
➢list_libs : checks if all the required library files are sourced or not and lists the sourced files.
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