Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
It is the process of creating the clock path from clock source to clock sinks.
The main goals of CTS are :
- distributes clock to all sequential cells through entire design.
- balances skew and minimizes insertion delay by proper buffering.
- should meet timing and power requirement.
- to meet design rule constraints (DRC) like max. trans, max. cap , max. fanout
It begins at SDC defined clock (clock source) and ends at sinks. Sinks are the pins of cells that receives clock, basically defined as end points.
Inputs for CTS are :
1. clockspec.tcl
- contains target skew.
- contains min. delay and max. delay.
- buffers/inverters required for building clock tree.
- NDR (Non Default Rules) like double spacing, double
width etc..,
- CTS exceptions.
- Type of tree to be built.
- max. trans, max. cap and max. fanout for clock.
2. .def of placement.
(*H-tree is the mostly
used algorithm for clock tree synthesis)
Clock nets are the most sensitive and high fanout nets. So, NDR are applied after completion of placement stage in order to avoid crosstalk and electron migration problems that may arise with clock build in CTS stage i.e., after clock propagation.
Non-Default rules are user-defined rules like double/triple width (avoids electron migration), double/triple spacing (avoids crosstalk), shielding etc.., It hardens the clock.
Clock signal is routed
first when compared to that of signal nets(data) as those nets are high fanout
nets and so, they require more routing resources. If the signal routing is
before CTS, there may be the possibility of crosstalk and congestion as the
required routing resources become limited.
Buffers are added for
balancing skew and minimizing the insertion delay.
In MPCTS/MSCTS (CTS algorithm), Clock distribution is done through tap points that gets clock signal from clock source and distributes uniformly. Buffers are to be added on the trunks for increasing drive strength. These buffers are called as "Anchor buffers". They can drive >= 1000 microns.
MPCTS: Multi Point CTS
MSCTS: Multi Source CTS
Clock Tree optimization done by
- buffer insertion
- gate sizing
- buffer relocation
- level adjustment
- HFN synthesis
- clock is to be shielded to avoid coupling of noise to
other signals as clock is a high switching net (aggressor).
- hold violation is to be fixed first and then setup
violations.
Clock exceptions :
- stop pins:
clock won't propagate after this pin.
- exclude/ignore pins:
not considered for clock propagation.
- float pins:
same as stop pin but internal clock latency of it is considered for clock
tree i.e., clock pin of IP's.
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