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Physical Design Flow

Physical Design  is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team).  The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
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Routing



It is the process of creating physical connections to all clock and signal pins based on logical connectivity. Moreover, this stage is meant for signal routing.
Routing deals with 4 steps.
1. Global Routing
2. Track Assignment
3. Detailed Routing
4. Search and Repair

Global Routing :
  • Assigns layers required for connectivity and finds the nearest path between the cells of the design by dividing core area into small cells called "G-cells". Avoids congested global cells while minimizing detours.
  • Global routing cells are logic cells based on average height of the cell.
  • They don't exist physically.
Track Assignment :
  • Assigns each net to a specific task based on global routing and actual metal traces are laid down.
  • Tries to make long, straight traces to avoid number of vias.

Detailed Routing :

  • Tries to fix all DRC violations after track assignment using a fixed size small area known as "Switch Box (Sbox)".
  • Sbox contains several g-cells.

Search and Repair :

  • Fixes remaining DRC violations through multiple iterative loops using progressively larger sbox sizes.
  • Locates shorts and spacing violations and reroutes the signals in the affected areas.


Among power routing, clock routing and signal routing, the sequence to be followed is:
1. power routing(Power planning)
2. clock routing(CTS)
3. signal routing(Routing)
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