Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
Power planning is nothing but creating power
mesh through the entire core area in order to provide the power to macros and
standard cells within the I-R limit. It is done as a part of floor planning.
In any IC, power
planning is done in higher metal layers because they have very less I-R drop.
It is because the higher metals are less resistive.
Since the width of those
metal layers is more, its resistance is less.
It can be explained by:
R = (ρ*length)/Area
Eg: For a chip having 9
metal layers, layers 8 and 9 are used in power planning (if the design is having single voltage source along with ground)
This concept includes
power pads, core rings, straps, rails.
Power pad : It is used to provide power supply from
source to the entire chip i.e., to core rings. It is defined with respect to
the full chip owner.
Power rings : Carries power around the core/IC/chip.
(*But now a days, bumps
are used instead of rings)
Straps : Carries Vdd & Vss across the chip from rings.
(*Straps is nothing but a combination of Vdd & Vss)
Rails : Carries Vdd & Vss to blocks through horizontal
metal.
But now a days, power to the design is supplied through Bumps. Bumps get power from primary source and spreads it through the design (in the manner of equal distribution). Metal Redistribution Layer can be used in such cases.
Power planning issues:
1. I-R drop
2. Ground bounce
3. EM violations
1. I-R drop:
It is defined as the
drop in voltage occurs due to the resistance of metal.
It is of two types:
a. Static I-R
drop: The voltage drop
due to the wire resistance irrespective of the cell switching is called as
static I-R drop.
b. Dynamic I-R
drop: It is occurred due
to switching of the cells
2. Ground bounce
(power bounce):
When a lot of
transistors are switching at the same time i.e., from 0 to 1, there may be
a possibility that some charge may leak through it which leads ground voltage
to jump to some active voltage( > Vil ).
3. EM violations:
Because of high current
density, electron may move from one place to another place.
Overcomes:
For I-R drop:
-power routing should be
done from top layer
-increase the number of
power straps
-increase the width of
the metal
-adding de-caps
-using low power techniques.For EM
violations:
-double width
-downsizing the cells
-metal slotting
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