Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
The following cells are
preferred as special cells.
1. End-cap cells
2. Tap cells
3. Tie cells
4. De-cap cells
5. Spare cells
6. Filler cells
Cells other than fillers are also referred as "Preplaced cells" and cells other than spares are referred as "Physical only cells".
Tap cells : These are used to reduce latch up problem and to provide continuity between macros.
End-cap cells : These defines us the end of the row, avoids damage of cells at end of the row and resolves power issues. These also avoids well proximity effect.
De-cap cells : Used for charge sharing i.e., they provide charge to their neighbor cells in order to avoid I-R drop. Also called De-coupling CAPacitors.
Tie cells : Provides constant Vdd( when connected to logic 1) or constant gnd( when connected to logic 0).
Spare cells :
- Contains combinational logic and used to enhance the
logic of the cells if required( future use).
- Spare cells are extra gates (And, Nor, Xor, Inverter etc.,) which are included in the layout but are functionally not connected
(or) used during initial design phase.
- If the functional change is required late in the design cycle, the layout can be modified (routing or metal mask changes only) to take advantage of these spare cells.
Filler cells : After routing, if the core still contains the free area, then these cells are used to fill the area in order to achieve 100% utilization.
ESD cells : Used to surpass the effects from electrostatic discharge .
The main problem in CMOS
is Latch up. It can be suppressed by:
1. Guard rings
2. Tap cells
3. SOI (Silicon On
Insulator)
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