Floorplan

Floorplanning :

It is the first step of physical design flow that takes care of pin placement, macro placement etc.., using the area intelligently.

But before that, we should know about a concept called "Partitioning".

Partitioning refers to the division of full chip into various parts, called as partitions (or) blocks (or) tiles in which each partition acts as a sub-chip. Each sub-chip contains macros, standard cells etc..,

Macro is a memory/intellectual property.

All memories are macros but all macros are not memories. Ex. PLL etc..,

Types of Macros:

1. Memories - RAM

                     - ROM

2. PLL/DLL

3. DAC/ADC

4. DSP cores

5. ARM cores

6. Graphic cores

 

The process of floorplanning is as follows:

Define core area and die area
⇓
Define i/p and o/p ports
⇓
Place macros
⇓
Hallos
⇓
Blockages
⇓
Power planning

 

Defining the die area and core area is carried out by the tool with reference to the synthesized netlist.

Standard cells are used in designing of chip. The significance of these standard cells is its width can be varied but height(length) can be fixed.

Floorplanning takes care of macro and port placement. Power planning is done as a part of floor planning which provides the power to the cells, blocks etc.., within the given I-R drop limit.

Core area can be calculated by:

The important factors in the floorplanning are

1. Aspect Ratio

2. Utilization

Aspect Ratio : The ratio of height of the cell to the width of the cell.

Utilisation : The core area utilised for the placement of macros, standard cells etc.., in terms of percentage. The remaining area is used for routing.

Basically floorplan can be classified;

Based on complexity:

1. Flat - entire chip is designed by a single person

2. Hierarchical - full chip is further divided into partitions

Based on portioning:

1. Channeled

2. Abutted - no channel b/w the blocks

3. Both - both the designs are included in this.

Based on design limitations:

1. core limited design - chip size is limited by core size.

2. pad limited design - chip size is limited by the pad area of the design.

Guidelines for floorplanning :

1. Macros should be placed near the boundaries.

2. Same family macros should be placed nearby.

3. Proper spacing is to be considered.

4. Flyline (or) flightline analysis (connectivity b/w macros).

5. Avoid criss-cross flightlines.

6. Proper alignment of macros should be done after placing them.

7. Orientation.

8. Avoid notches in the floorplan.

9. Pins of the macros should be towards core area.

Hallos :

Also called as Keep-out margin.

It is used to block the area around the macro in order to avoid the placement of standard cells on the pins at placement stage. Also used for n-well discontinuity between macro and standard cell.

It also overcomes well-proximity effect.

Blockage :

It blocks the particular area in order to avoid the placement of other cells. It is explained detailed in Blockage.

Placement of physical cells is also to be done in this stage. These cells include End-cap cells and Tap cells.

The cells that are used before placement stage are known as Preplaced cells.

The design view is of 3 types.

1. FRAM: logic is not visible

2. CEL: also called as abstract view. logic of the standard cell is visible

3. DESIGN: logic can be modified as well as viewed