Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
Floorplanning : It is the first step of physical design flow that takes care of pin placement, macro placement etc.., using the area intelligently. But before that, we should know about a concept called "Partitioning". Partitioning refers to the division of full chip into various parts, called as partitions (or) blocks (or) tiles in which each partition acts as a sub-chip. Each sub-chip contains macros, standard cells etc.., Macro is a memory/intellectual property. All memories are macros but all macros are not memories. Ex. PLL etc.., Types of Macros: 1. Memories - RAM - ROM 2. PLL/DLL 3. DAC/ADC 4. DSP cores 5. ARM cores 6. Graphic cores The process of floorplanning is as follows: Define core area and die area ⇓ Define i/p and o/p ports ⇓ Place macros ⇓ Hallos ⇓ Blockages ⇓ Power planning Defining the die area and core area is carried out by the t...