Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
Power planning is nothing but creating power mesh through the entire core area in order to provide the power to macros and standard cells within the I-R limit. It is done as a part of floor planning. In any IC, power planning is done in higher metal layers because they have very less I-R drop. It is because the higher metals are less resistive. Since the width of those metal layers is more, its resistance is less. It can be explained by: R = (ρ*length)/Area Eg: For a chip having 9 metal layers, layers 8 and 9 are used in power planning (if the design is having single voltage source along with ground) This concept includes power pads, core rings, straps, rails. Power pad : It is used to provide power supply from source to the entire chip i.e., to core rings. It is defined with respect to the full chip owner. Power rings : Carries power around the core/IC/chip. (*But now a days, bumps are used instead of rings) Straps : Carries Vdd & Vss a...