Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
The Inputs for Physical Design are: .v or .vg (Synthesized Netlist) : It contains logic interconnection of gates for all cells (std. cells, macros..,). Contains list of nets (*Net : Collection of 2 or more interconnected logic components). .tf (Technology File) : Manufacturing grid Physical characteristics (min. height, min. width, min. area) Electrical characteristics (current density) of layers and vias. Colours and Patterns. Units and Precisions. Physical design rules like wire-wire spacing, min. width b/w layer and via. Stipple patterns. Line styles. Device characteristics. Coupling capacitances. Capacitance models. Dielectric values and thickness. .sdc (Synopsys Design Constraints) : Timing, Design and Area constraints. Operating conditions. Logic assignments Multi voltage & power optimization constraints. Clock definitions (creating master...