Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
It is the process of placing pre-designed cells (std. cells) in a legalized manner such that some objective function is optimized. Tool takes care of power, timing, congestion etc.., while placement. Steps of placement : Coarse placement Legalized placement Detailed placement Coarse placement : placer engine places all the standard cells inside the core area from outside without any legalization. Legalized placement : places std. cells exactly on the site rows and without any overlaps. Detailed placement : iterative placement and optimization. Sanity checks before going to placement stage : All macros and ports are to be placed properly and fixed. Power routing should be done. Preplaced cells should be inserted. checking the availability of scan chain information as scan chain reordering is to be done at this stage. (* Scan chain : logical connectivity of cells in order to form a unified shift register. It is g...