Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
1. Static Power Dissipation - Due to leakage currents (without any operation) (standby mode) 2. Dynamic Power Dissipation - Due to switching (switching mode) Total power dissipation = Static power diss. + Dynamic power diss. Static power dissipation is due to: a) Gate oxide leakage currents b) Junction leakage currents c) Sub-threshold currents Dynamic power dissipation : a) switching p.d. b) short circuit p.d. c) glitching p.d. - large delays Power reduction techniques in CMOS 1. Reduce the supply voltage 2. Using variable clock frequencies and operating voltages. 3. First increase the performance of the circuit (by adding components in parallel) and then reduce the voltage of the circuit. *If voltage is reduced before increasing the performance, the delay of the circuit increases. 4. Clock gating and power gating. Dynamic power dissipation can be reduced by reducing: a) Clock frequency ...