explorePD

Setup analysis :   AT <= RT Setup slack :   RT - AT where AT = T L  + T CK_Q  + T COMBO RT = T - T S  + T C Hold analysis :   AT >= RT Hold slack :   AT - RT where AT = T L  + T CK_Q  + T COMBO RT = T H  + T C Here AT = Arrival Time RT = Required Time T L  = Launch Time T C  = Capture Time T S  = Setup Time T H  = Hold Time T = Time period (If the above conditions of the slack were not met, then they are said to be violated. It may cause timing failure of the design which in-turn causes damage of the chip.) *Tool goes for the worst case while analyzing setup slack and best case for hold slack analysis. Hence, it considers max. delay in data path for setup slack analysis and min. delay in data path for hold slack analysis. *If there is uncertainty(U), then tool considers RT - U  for setup slack RT + U  for hold slack because of worst and best case...

STA(Static Time Analysis) : It is the process of analysing the timing constraints of the design without any simulation/switching. Basically, Timing analysis is of 2 types. 1. STA - Static Timing Analysis 2. DTA - Dynamic Timing Analysis Setup time:  min. amount of time for which the data signal is to be stable before the next active clock edge. Hold time:  min. amount of time for which the data signal is to be stable after the first active clock edge. Launch flop :  flop that is responsible for launching the data. Capture flop :  flop that is responsible for capturing the data. Launch clock :  clock responsible for making launch flop active. Capture clock :  clock responsible for making capture flop active. Launch time :  time taken for launching the data. Capture time :  time taken for capturing the data. Data path :  path of data signal (or) path starting from common point of clock network to th...

It is the process of creating physical connections to all clock and signal pins based on logical connectivity. Moreover, this stage is meant for signal routing. Routing deals with 4 steps. 1. Global Routing 2. Track Assignment 3. Detailed Routing 4. Search and Repair Global Routing  : Assigns layers required for connectivity and finds the nearest path between the cells of the design by dividing core area into small cells called "G-cells". Avoids congested global cells while minimizing detours. Global routing cells are logic cells based on average height of the cell. They don't exist physically. Track Assignment  : Assigns each net to a specific task based on global routing and actual metal traces are laid down. Tries to make long, straight traces to avoid number of vias. Detailed Routing  : Tries to fix all DRC violations after track assignment using a fixed size small area known as "Switch Box (Sbo...

It is the process of creating the clock path from clock source to clock sinks. The main goals of CTS are : distributes clock to all sequential cells through entire design. balances skew and minimizes insertion delay by proper buffering. should meet timing and power requirement. to meet design rule constraints (DRC) like max. trans, max. cap , max. fanout It begins at SDC defined clock (clock source) and ends at sinks. Sinks are the pins of cells that receives clock, basically defined as end points. Inputs for CTS  are : 1. clockspec.tcl contains target skew. contains min. delay and max. delay. buffers/inverters required for building clock tree. NDR (Non Default Rules) like double spacing, double width etc.., CTS exceptions. Type of tree to be built. max. trans, max. cap and max. fanout for clock. 2. .def of placement. (*H-tree is the mostly used algorithm for clock tree synthesis) Clock nets are the most sensitive and high fanout nets. So, NDR are applied after...