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Physical Design Flow

Physical Design  is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team).  The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
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Scan chain reordering

Scan chain is detached and reordered without any change in functionality. It helps in reducing congestion. Also helps in meeting timing and reducing IR drop as the number of nets gets reduced. Flops are converted into scan enabled flip flops and stitched into chains at synthesis stage. It is done by DFT team. SEFF Internal of SEFF SEFF before Stitching After reordering, the number of flops in the scan chain should be same as before. First and last flops may change after reordering. Flops of different scan chains are exchanged and reordered by considering partition. Partition is a group of "scandef chains" that may exchange flops during reordering. Lockup latches and multiplexers breakup scan chains further into "reordering buckets". Reordering happens within these buckets only and the flops that are to be reordered are kept as floating in scanDEF.
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Clock Re-convergence Pessimism Removal

C lock  R e-convergence  P essimism  R emoval. Also called as CPPR . Let's consider a buffer that is placed in common path (both data path and clock path). Tool calculates max. delays for setup calculation and min. delays for hold (worst and best case analysis). When comes to OCV analysis, tool further considers, max. for data path and min. for clock path during setup analysis. max. for clock path and min. for data path during hold analysis. So, buffer placed in common path now has 2 values i.e., max. and min. values. As we know, a cell can't have two different values at a particular instant of time. Thereby we calculates the buffer value as, CRPR = Max. value - min. value While performing STA, for setup analysis, CRPR is added in RT whereas in hold analysis, it is subtracted from RT. RT + CRPR (for setup) RT - CRPR (for hold) Example regarding CRPR is shown above. For above figure, CRPR = 1ns ...
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Power Dissipation

1. Static Power Dissipation -  Due to leakage currents (without any operation) (standby mode) 2. Dynamic Power Dissipation -  Due to switching (switching mode)   Total power dissipation = Static power diss. + Dynamic power diss. Static power dissipation  is due to: a) Gate oxide leakage currents b) Junction leakage currents c) Sub-threshold currents Dynamic power dissipation : a) switching p.d. b) short circuit p.d. c) glitching p.d. - large delays   Power reduction techniques in CMOS 1. Reduce the supply voltage 2. Using variable clock frequencies and operating voltages. 3. First increase the performance of the circuit (by adding components in parallel) and then reduce the voltage of the circuit.  *If voltage is reduced before increasing the performance, the delay of the circuit increases. 4. Clock gating and power gating.   Dynamic power dissipation   can be reduced by reducing: a) Clock frequency ...
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