Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
File Management : Command Description :w To save the file which is in write mode :w! To overwrite/save file which is in read mode :wq To save and quit :q To quit without saving :q! To quit the modified but unsaved file. :wa To save all files :qa To quit all files Line settings : Command Description :set nu Sets numbers for lines :set nonu Removes line numbers :set hls Highlights the search pattern :set ic Ignore case :set is Incremental search :set nowrap No wrapping of text in a file :set wrap Wrap the text in a file :set relativenumber Sets the relative numbers :set norelativenu...