Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
Switching of a signal in one net can interfere the signal in neighboring net due to coupling capacitance formed between the metals. This is referred as " CrossTalk" . The affecting net is called as " Aggressor " whereas the net being affected is called as "V ictim ". There are 2 types of effects caused by crosstalk. Crosstalk Noise : because of glitch (steady victim) Crosstalk Delay : change in timing of the victim (switching victim) Crosstalk Noise : This is because of glitch formed on victim. Here aggressor is switching signal whereas victim is a steady signal (either constant 1 or 0). The magnitude of the glitch depends on coupling capacitance between the aggressor and victim slew of the aggressor net If the magnitude of the glitch is large enough, then the fanout cell gets a different logic value that results in functionality error. Types of Glitches : When victim is at steady low Rise glitch : when ag...