Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
It is used to block the particular core area to avoid the placement of other cells in that area or to block the routing resources. Types of Blockages: 1. Placement blockage 2. Routing blockage Placement blockage: It blocks the selected area from placement of other cells. Routing blockage: It blocks the particular routing resources (or) area from routing. Placement blockage is further divided into: Hard blockage: It doesn't allow any other cell to sit in the blocked area Soft blockage: It allows only the inverters and buffers through this to sit in the selected area Partial blockage: It allows the inverters, buffers and standard cells to sit in the remaining area other than provided area to be blocked. It should be given in % Eg: If partial blockage is given as 20%, then 20% of the blockage area is blocked and remaining 80% area allowed to sit.