Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
Setup analysis : AT <= RT Setup slack : RT - AT where AT = T L + T CK_Q + T COMBO RT = T - T S + T C Hold analysis : AT >= RT Hold slack : AT - RT where AT = T L + T CK_Q + T COMBO RT = T H + T C Here AT = Arrival Time RT = Required Time T L = Launch Time T C = Capture Time T S = Setup Time T H = Hold Time T = Time period (If the above conditions of the slack were not met, then they are said to be violated. It may cause timing failure of the design which in-turn causes damage of the chip.) *Tool goes for the worst case while analyzing setup slack and best case for hold slack analysis. Hence, it considers max. delay in data path for setup slack analysis and min. delay in data path for hold slack analysis. *If there is uncertainty(U), then tool considers RT - U for setup slack RT + U for hold slack because of worst and best case...