Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
STA(Static Time Analysis) : It is the process of analysing the timing constraints of the design without any simulation/switching. Basically, Timing analysis is of 2 types. 1. STA - Static Timing Analysis 2. DTA - Dynamic Timing Analysis Setup time: min. amount of time for which the data signal is to be stable before the next active clock edge. Hold time: min. amount of time for which the data signal is to be stable after the first active clock edge. Launch flop : flop that is responsible for launching the data. Capture flop : flop that is responsible for capturing the data. Launch clock : clock responsible for making launch flop active. Capture clock : clock responsible for making capture flop active. Launch time : time taken for launching the data. Capture time : time taken for capturing the data. Data path : path of data signal (or) path starting from common point of clock network to th...