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SANITY CHECKS We check mainly the following input files: 1. Netlist 2.  SDC files 3. Library files 4. Design information The following commands are used for performing sanity checks and generation of the reports: check_design check_timing check_library check_legality check_tlu_plus_files check_mv_design report_constraints report_timing report_qor ➢check_design :  checks the compatibility of the design and checks the potential problems like unloaded input ports and undriven output ports, mismatched pin count, multidriven nets etc.., It also reports unification problems. ➢ check_timing  :   checks for any unconstrained paths as PnR tool optimizes the constrained paths only. ➢ check_library  : performs the consistency checks within logical and physical libraries. It checks library qualities in physical library quality logic (vs) physical library consistency logic (vs) logical library consistency and shows if any cells missing, missing/mismatched pins.  In...

  The Inputs for Physical Design are: .v or .vg (Synthesized Netlist) : It contains logic interconnection of gates for all cells (std. cells, macros..,). Contains list of nets (*Net : Collection of 2 or more interconnected logic components). .tf (Technology File) : Manufacturing grid Physical characteristics (min. height, min. width, min. area) Electrical characteristics (current density) of layers and vias. Colours and Patterns. Units and Precisions. Physical design rules like wire-wire spacing, min. width b/w layer and via. Stipple patterns. Line styles. Device characteristics. Coupling capacitances. Capacitance models. Dielectric values and thickness. .sdc (Synopsys Design Constraints) : Timing, Design and Area constraints. Operating conditions. Logic assignments Multi voltage & power optimization constraints. Clock definitions (creating master...

SYNTHESIS Transformation of idea into manufacturable device to carry out an intended function. Types of Synthesis : 1.  Behavioral Synthesis           - specifications into RTL code. 2.  Logical Synthesis           - RTL code to Gate level netlist (.v) 3.  Physical Synthesis           - .v to .gdsii (Graphical Data Stream/System Information Interchange)           Completing a round of logical synthesis, Floorplan is done along with rough placement of std. cells. The output of this stage (in the form of .def) is given back to the synthesis tool for better compilation, mostly in terms of area and timing optimization. Its also called  Physical Synthesis Normally, with respect to synopsys tools, Design Compiler is used for logical synthesis and DC Topo is used for Physical Synthesis. .gdsii contains the 3D view info. of design(& cells) that defines...

Physical Design  is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team).  The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...

ASIC Flow : System Specification (idea) ⇓ Architectural Design (data flow) ⇓ Functional Design ⇓ RTL Design and Verification ⇓ Synthesis ⇓ Physical Design ⇓ SignOff (PV, STA , LEC ..) ⇓ Fabrication ⇓ Testing ⇓ Packaging ⇓ Final Chip VLSI designing is divided into front end and back end. Till synthesis stage, comes under frond end designing. Remaining steps are treated as back end. After synthesis and before physical design, there is DFT team for testing of connectivity of the cells, inserts scan chains etc.., DFT team also tests the chip after fabrication of the chip. Based on the market survey results, we will finalize our system specifications. Architectural design :  Gives dataflow diagram required to design the chip. RTL design :  Writes the RTL code by using Verilog, VHDL, System Verilog, UVM etc.., Design Verification :   Verifies the consistency of the given RTL code. Synthesis :   converts RTL code into gate level netlist. Physical D...