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It is the process of placing pre-designed cells (std. cells) in a legalized manner such that some objective function is optimized. Tool takes care of power, timing, congestion etc.., while placement. Steps of placement : Coarse placement Legalized placement Detailed placement Coarse placement :  placer engine places all the standard cells inside the core area from outside without any legalization. Legalized placement :  places std. cells exactly on the site rows and without any overlaps. Detailed placement :  iterative placement and optimization. Sanity checks before going to placement stage  : All macros and ports are to be placed properly and fixed. Power routing should be done. Preplaced cells should be inserted. checking the availability of scan chain information as scan chain reordering is to be done at this stage. (* Scan chain :  logical connectivity of cells in order to form a unified shift register. It is g...

  Power planning is nothing but creating power mesh through the entire core area in order to provide the power to macros and standard cells within the I-R limit. It is done as a part of floor planning. In any IC, power planning is done in higher metal layers because they have very less I-R drop. It is because the higher metals are less resistive. Since the width of those metal layers is more, its resistance is less. It can be explained by:   R = (ρ*length)/Area Eg: For a chip having 9 metal layers, layers 8 and 9 are used in power planning (if the design is having single voltage source along with ground) This concept includes power pads, core rings, straps, rails. Power pad :  It is used to provide power supply from source to the entire chip i.e., to core rings. It is defined with respect to the full chip owner. Power rings :  Carries power around the core/IC/chip. (*But now a days, bumps are used instead of rings) Straps :  Carries Vdd & Vss a...

The following cells are preferred as special cells. 1. End-cap cells 2. Tap cells 3. Tie cells 4. De-cap cells 5. Spare cells 6. Filler cells Cells other than fillers are also referred as " Preplaced cells " and cells other than spares are referred as "Physical only cells". Tap cells :  These are used to reduce latch up problem and to provide continuity between macros. End-cap cells :  These defines us the end of the row, avoids damage of cells at end of the row and resolves power issues. These also avoids well proximity effect. De-cap cells :  Used for charge sharing i.e., they provide charge to their neighbor cells in order to avoid I-R drop. Also called De-coupling CAPacitors. Tie cells :  Provides constant Vdd( when connected to logic 1) or constant gnd( when connected to logic 0). Spare cells : Contains combinational logic and used to enhance the logic of the cells if required( future use). Spare cells are extra gates (An...

  It is used to block the particular core area to avoid the placement of other cells in that area or to block the routing resources. Types of Blockages: 1. Placement blockage 2. Routing blockage Placement blockage:  It blocks the selected area from placement of other cells. Routing blockage:  It blocks the particular routing resources (or) area from routing.   Placement blockage is further divided into: Hard blockage:  It doesn't allow any other cell to sit in the blocked area Soft blockage:  It allows only the inverters and buffers through this to sit in the selected area Partial blockage:  It allows the inverters, buffers and standard cells to sit in the remaining area other than provided area to be blocked. It should be given in % Eg: If partial blockage is given as 20%, then 20% of the blockage area is blocked and remaining 80% area allowed to sit.

Floorplanning : It is the first step of physical design flow that takes care of pin placement, macro placement etc.., using the area intelligently. But before that, we should know about a concept called  "Partitioning". Partitioning refers to the division of full chip into various parts, called as partitions (or) blocks (or) tiles in which each partition acts as a sub-chip. Each sub-chip contains macros, standard cells etc.., Macro is a memory/intellectual property. All memories are macros but all macros are not memories. Ex. PLL etc.., Types of Macros: 1. Memories - RAM                      - ROM 2. PLL/DLL 3. DAC/ADC 4. DSP cores 5. ARM cores 6. Graphic cores   The process of floorplanning is as follows: Define core area and die area ⇓ Define i/p and o/p ports ⇓ Place macros ⇓ Hallos ⇓ Blockages ⇓ Power planning   Defining the die area and core area is carried out by the t...

SANITY CHECKS We check mainly the following input files: 1. Netlist 2.  SDC files 3. Library files 4. Design information The following commands are used for performing sanity checks and generation of the reports: check_design check_timing check_library check_legality check_tlu_plus_files check_mv_design report_constraints report_timing report_qor ➢check_design :  checks the compatibility of the design and checks the potential problems like unloaded input ports and undriven output ports, mismatched pin count, multidriven nets etc.., It also reports unification problems. ➢ check_timing  :   checks for any unconstrained paths as PnR tool optimizes the constrained paths only. ➢ check_library  : performs the consistency checks within logical and physical libraries. It checks library qualities in physical library quality logic (vs) physical library consistency logic (vs) logical library consistency and shows if any cells missing, missing/mismatched pins.  In...

  The Inputs for Physical Design are: .v or .vg (Synthesized Netlist) : It contains logic interconnection of gates for all cells (std. cells, macros..,). Contains list of nets (*Net : Collection of 2 or more interconnected logic components). .tf (Technology File) : Manufacturing grid Physical characteristics (min. height, min. width, min. area) Electrical characteristics (current density) of layers and vias. Colours and Patterns. Units and Precisions. Physical design rules like wire-wire spacing, min. width b/w layer and via. Stipple patterns. Line styles. Device characteristics. Coupling capacitances. Capacitance models. Dielectric values and thickness. .sdc (Synopsys Design Constraints) : Timing, Design and Area constraints. Operating conditions. Logic assignments Multi voltage & power optimization constraints. Clock definitions (creating master...

SYNTHESIS Transformation of idea into manufacturable device to carry out an intended function. Types of Synthesis : 1.  Behavioral Synthesis           - specifications into RTL code. 2.  Logical Synthesis           - RTL code to Gate level netlist (.v) 3.  Physical Synthesis           - .v to .gdsii (Graphical Data Stream/System Information Interchange)           Completing a round of logical synthesis, Floorplan is done along with rough placement of std. cells. The output of this stage (in the form of .def) is given back to the synthesis tool for better compilation, mostly in terms of area and timing optimization. Its also called  Physical Synthesis Normally, with respect to synopsys tools, Design Compiler is used for logical synthesis and DC Topo is used for Physical Synthesis. .gdsii contains the 3D view info. of design(& cells) that defines...

Physical Design  is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team).  The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...