explorePD

Setup analysis :   AT <= RT Setup slack :   RT - AT where AT = T L  + T CK_Q  + T COMBO RT = T - T S  + T C Hold analysis :   AT >= RT Hold slack :   AT - RT where AT = T L  + T CK_Q  + T COMBO RT = T H  + T C Here AT = Arrival Time RT = Required Time T L  = Launch Time T C  = Capture Time T S  = Setup Time T H  = Hold Time T = Time period (If the above conditions of the slack were not met, then they are said to be violated. It may cause timing failure of the design which in-turn causes damage of the chip.) *Tool goes for the worst case while analyzing setup slack and best case for hold slack analysis. Hence, it considers max. delay in data path for setup slack analysis and min. delay in data path for hold slack analysis. *If there is uncertainty(U), then tool considers RT - U  for setup slack RT + U  for hold slack because of worst and best case...

STA(Static Time Analysis) : It is the process of analysing the timing constraints of the design without any simulation/switching. Basically, Timing analysis is of 2 types. 1. STA - Static Timing Analysis 2. DTA - Dynamic Timing Analysis Setup time:  min. amount of time for which the data signal is to be stable before the next active clock edge. Hold time:  min. amount of time for which the data signal is to be stable after the first active clock edge. Launch flop :  flop that is responsible for launching the data. Capture flop :  flop that is responsible for capturing the data. Launch clock :  clock responsible for making launch flop active. Capture clock :  clock responsible for making capture flop active. Launch time :  time taken for launching the data. Capture time :  time taken for capturing the data. Data path :  path of data signal (or) path starting from common point of clock network to th...

It is the process of creating physical connections to all clock and signal pins based on logical connectivity. Moreover, this stage is meant for signal routing. Routing deals with 4 steps. 1. Global Routing 2. Track Assignment 3. Detailed Routing 4. Search and Repair Global Routing  : Assigns layers required for connectivity and finds the nearest path between the cells of the design by dividing core area into small cells called "G-cells". Avoids congested global cells while minimizing detours. Global routing cells are logic cells based on average height of the cell. They don't exist physically. Track Assignment  : Assigns each net to a specific task based on global routing and actual metal traces are laid down. Tries to make long, straight traces to avoid number of vias. Detailed Routing  : Tries to fix all DRC violations after track assignment using a fixed size small area known as "Switch Box (Sbo...

It is the process of creating the clock path from clock source to clock sinks. The main goals of CTS are : distributes clock to all sequential cells through entire design. balances skew and minimizes insertion delay by proper buffering. should meet timing and power requirement. to meet design rule constraints (DRC) like max. trans, max. cap , max. fanout It begins at SDC defined clock (clock source) and ends at sinks. Sinks are the pins of cells that receives clock, basically defined as end points. Inputs for CTS  are : 1. clockspec.tcl contains target skew. contains min. delay and max. delay. buffers/inverters required for building clock tree. NDR (Non Default Rules) like double spacing, double width etc.., CTS exceptions. Type of tree to be built. max. trans, max. cap and max. fanout for clock. 2. .def of placement. (*H-tree is the mostly used algorithm for clock tree synthesis) Clock nets are the most sensitive and high fanout nets. So, NDR are applied after...

It is the process of placing pre-designed cells (std. cells) in a legalized manner such that some objective function is optimized. Tool takes care of power, timing, congestion etc.., while placement. Steps of placement : Coarse placement Legalized placement Detailed placement Coarse placement :  placer engine places all the standard cells inside the core area from outside without any legalization. Legalized placement :  places std. cells exactly on the site rows and without any overlaps. Detailed placement :  iterative placement and optimization. Sanity checks before going to placement stage  : All macros and ports are to be placed properly and fixed. Power routing should be done. Preplaced cells should be inserted. checking the availability of scan chain information as scan chain reordering is to be done at this stage. (* Scan chain :  logical connectivity of cells in order to form a unified shift register. It is g...

  Power planning is nothing but creating power mesh through the entire core area in order to provide the power to macros and standard cells within the I-R limit. It is done as a part of floor planning. In any IC, power planning is done in higher metal layers because they have very less I-R drop. It is because the higher metals are less resistive. Since the width of those metal layers is more, its resistance is less. It can be explained by:   R = (ρ*length)/Area Eg: For a chip having 9 metal layers, layers 8 and 9 are used in power planning (if the design is having single voltage source along with ground) This concept includes power pads, core rings, straps, rails. Power pad :  It is used to provide power supply from source to the entire chip i.e., to core rings. It is defined with respect to the full chip owner. Power rings :  Carries power around the core/IC/chip. (*But now a days, bumps are used instead of rings) Straps :  Carries Vdd & Vss a...

The following cells are preferred as special cells. 1. End-cap cells 2. Tap cells 3. Tie cells 4. De-cap cells 5. Spare cells 6. Filler cells Cells other than fillers are also referred as " Preplaced cells " and cells other than spares are referred as "Physical only cells". Tap cells :  These are used to reduce latch up problem and to provide continuity between macros. End-cap cells :  These defines us the end of the row, avoids damage of cells at end of the row and resolves power issues. These also avoids well proximity effect. De-cap cells :  Used for charge sharing i.e., they provide charge to their neighbor cells in order to avoid I-R drop. Also called De-coupling CAPacitors. Tie cells :  Provides constant Vdd( when connected to logic 1) or constant gnd( when connected to logic 0). Spare cells : Contains combinational logic and used to enhance the logic of the cells if required( future use). Spare cells are extra gates (An...

  It is used to block the particular core area to avoid the placement of other cells in that area or to block the routing resources. Types of Blockages: 1. Placement blockage 2. Routing blockage Placement blockage:  It blocks the selected area from placement of other cells. Routing blockage:  It blocks the particular routing resources (or) area from routing.   Placement blockage is further divided into: Hard blockage:  It doesn't allow any other cell to sit in the blocked area Soft blockage:  It allows only the inverters and buffers through this to sit in the selected area Partial blockage:  It allows the inverters, buffers and standard cells to sit in the remaining area other than provided area to be blocked. It should be given in % Eg: If partial blockage is given as 20%, then 20% of the blockage area is blocked and remaining 80% area allowed to sit.

Floorplanning : It is the first step of physical design flow that takes care of pin placement, macro placement etc.., using the area intelligently. But before that, we should know about a concept called  "Partitioning". Partitioning refers to the division of full chip into various parts, called as partitions (or) blocks (or) tiles in which each partition acts as a sub-chip. Each sub-chip contains macros, standard cells etc.., Macro is a memory/intellectual property. All memories are macros but all macros are not memories. Ex. PLL etc.., Types of Macros: 1. Memories - RAM                      - ROM 2. PLL/DLL 3. DAC/ADC 4. DSP cores 5. ARM cores 6. Graphic cores   The process of floorplanning is as follows: Define core area and die area ⇓ Define i/p and o/p ports ⇓ Place macros ⇓ Hallos ⇓ Blockages ⇓ Power planning   Defining the die area and core area is carried out by the t...