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Scan chain is detached and reordered without any change in functionality. It helps in reducing congestion. Also helps in meeting timing and reducing IR drop as the number of nets gets reduced. Flops are converted into scan enabled flip flops and stitched into chains at synthesis stage. It is done by DFT team. SEFF Internal of SEFF SEFF before Stitching After reordering, the number of flops in the scan chain should be same as before. First and last flops may change after reordering. Flops of different scan chains are exchanged and reordered by considering partition. Partition is a group of "scandef chains" that may exchange flops during reordering. Lockup latches and multiplexers breakup scan chains further into "reordering buckets". Reordering happens within these buckets only and the flops that are to be reordered are kept as floating in scanDEF.

C lock  R e-convergence  P essimism  R emoval. Also called as CPPR . Let's consider a buffer that is placed in common path (both data path and clock path). Tool calculates max. delays for setup calculation and min. delays for hold (worst and best case analysis). When comes to OCV analysis, tool further considers, max. for data path and min. for clock path during setup analysis. max. for clock path and min. for data path during hold analysis. So, buffer placed in common path now has 2 values i.e., max. and min. values. As we know, a cell can't have two different values at a particular instant of time. Thereby we calculates the buffer value as, CRPR = Max. value - min. value While performing STA, for setup analysis, CRPR is added in RT whereas in hold analysis, it is subtracted from RT. RT + CRPR (for setup) RT - CRPR (for hold) Example regarding CRPR is shown above. For above figure, CRPR = 1ns ...

1. Static Power Dissipation -  Due to leakage currents (without any operation) (standby mode) 2. Dynamic Power Dissipation -  Due to switching (switching mode)   Total power dissipation = Static power diss. + Dynamic power diss. Static power dissipation  is due to: a) Gate oxide leakage currents b) Junction leakage currents c) Sub-threshold currents Dynamic power dissipation : a) switching p.d. b) short circuit p.d. c) glitching p.d. - large delays   Power reduction techniques in CMOS 1. Reduce the supply voltage 2. Using variable clock frequencies and operating voltages. 3. First increase the performance of the circuit (by adding components in parallel) and then reduce the voltage of the circuit.  *If voltage is reduced before increasing the performance, the delay of the circuit increases. 4. Clock gating and power gating.   Dynamic power dissipation   can be reduced by reducing: a) Clock frequency ...

Setup analysis :   AT <= RT Setup slack :   RT - AT where AT = T L  + T CK_Q  + T COMBO RT = T - T S  + T C Hold analysis :   AT >= RT Hold slack :   AT - RT where AT = T L  + T CK_Q  + T COMBO RT = T H  + T C Here AT = Arrival Time RT = Required Time T L  = Launch Time T C  = Capture Time T S  = Setup Time T H  = Hold Time T = Time period (If the above conditions of the slack were not met, then they are said to be violated. It may cause timing failure of the design which in-turn causes damage of the chip.) *Tool goes for the worst case while analyzing setup slack and best case for hold slack analysis. Hence, it considers max. delay in data path for setup slack analysis and min. delay in data path for hold slack analysis. *If there is uncertainty(U), then tool considers RT - U  for setup slack RT + U  for hold slack because of worst and best case...

STA(Static Time Analysis) : It is the process of analysing the timing constraints of the design without any simulation/switching. Basically, Timing analysis is of 2 types. 1. STA - Static Timing Analysis 2. DTA - Dynamic Timing Analysis Setup time:  min. amount of time for which the data signal is to be stable before the next active clock edge. Hold time:  min. amount of time for which the data signal is to be stable after the first active clock edge. Launch flop :  flop that is responsible for launching the data. Capture flop :  flop that is responsible for capturing the data. Launch clock :  clock responsible for making launch flop active. Capture clock :  clock responsible for making capture flop active. Launch time :  time taken for launching the data. Capture time :  time taken for capturing the data. Data path :  path of data signal (or) path starting from common point of clock network to th...

It is the process of creating physical connections to all clock and signal pins based on logical connectivity. Moreover, this stage is meant for signal routing. Routing deals with 4 steps. 1. Global Routing 2. Track Assignment 3. Detailed Routing 4. Search and Repair Global Routing  : Assigns layers required for connectivity and finds the nearest path between the cells of the design by dividing core area into small cells called "G-cells". Avoids congested global cells while minimizing detours. Global routing cells are logic cells based on average height of the cell. They don't exist physically. Track Assignment  : Assigns each net to a specific task based on global routing and actual metal traces are laid down. Tries to make long, straight traces to avoid number of vias. Detailed Routing  : Tries to fix all DRC violations after track assignment using a fixed size small area known as "Switch Box (Sbo...

It is the process of creating the clock path from clock source to clock sinks. The main goals of CTS are : distributes clock to all sequential cells through entire design. balances skew and minimizes insertion delay by proper buffering. should meet timing and power requirement. to meet design rule constraints (DRC) like max. trans, max. cap , max. fanout It begins at SDC defined clock (clock source) and ends at sinks. Sinks are the pins of cells that receives clock, basically defined as end points. Inputs for CTS  are : 1. clockspec.tcl contains target skew. contains min. delay and max. delay. buffers/inverters required for building clock tree. NDR (Non Default Rules) like double spacing, double width etc.., CTS exceptions. Type of tree to be built. max. trans, max. cap and max. fanout for clock. 2. .def of placement. (*H-tree is the mostly used algorithm for clock tree synthesis) Clock nets are the most sensitive and high fanout nets. So, NDR are applied after...

It is the process of placing pre-designed cells (std. cells) in a legalized manner such that some objective function is optimized. Tool takes care of power, timing, congestion etc.., while placement. Steps of placement : Coarse placement Legalized placement Detailed placement Coarse placement :  placer engine places all the standard cells inside the core area from outside without any legalization. Legalized placement :  places std. cells exactly on the site rows and without any overlaps. Detailed placement :  iterative placement and optimization. Sanity checks before going to placement stage  : All macros and ports are to be placed properly and fixed. Power routing should be done. Preplaced cells should be inserted. checking the availability of scan chain information as scan chain reordering is to be done at this stage. (* Scan chain :  logical connectivity of cells in order to form a unified shift register. It is g...

  Power planning is nothing but creating power mesh through the entire core area in order to provide the power to macros and standard cells within the I-R limit. It is done as a part of floor planning. In any IC, power planning is done in higher metal layers because they have very less I-R drop. It is because the higher metals are less resistive. Since the width of those metal layers is more, its resistance is less. It can be explained by:   R = (ρ*length)/Area Eg: For a chip having 9 metal layers, layers 8 and 9 are used in power planning (if the design is having single voltage source along with ground) This concept includes power pads, core rings, straps, rails. Power pad :  It is used to provide power supply from source to the entire chip i.e., to core rings. It is defined with respect to the full chip owner. Power rings :  Carries power around the core/IC/chip. (*But now a days, bumps are used instead of rings) Straps :  Carries Vdd & Vss a...