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CrossTalk

Switching of a signal in one net can interfere the signal in neighboring net due to coupling capacitance formed between the metals. This is referred as " CrossTalk" . The affecting net is called as " Aggressor " whereas the net being affected is called as "V ictim ". There are 2 types of effects caused by crosstalk. Crosstalk Noise : because of glitch (steady victim) Crosstalk Delay : change in timing of the victim (switching victim) Crosstalk Noise : This is because of glitch formed on victim. Here aggressor is switching signal whereas victim is a steady signal (either constant 1 or 0). The magnitude of the glitch depends on coupling capacitance between the aggressor and victim slew of the aggressor net If the magnitude of the glitch is large enough, then the fanout cell gets a different logic value that results in functionality error. Types of Glitches : When victim is at steady low Rise glitch : when ag...

Scan chain reordering

Scan chain is detached and reordered without any change in functionality. It helps in reducing congestion. Also helps in meeting timing and reducing IR drop as the number of nets gets reduced. Flops are converted into scan enabled flip flops and stitched into chains at synthesis stage. It is done by DFT team. SEFF Internal of SEFF SEFF before Stitching After reordering, the number of flops in the scan chain should be same as before. First and last flops may change after reordering. Flops of different scan chains are exchanged and reordered by considering partition. Partition is a group of "scandef chains" that may exchange flops during reordering. Lockup latches and multiplexers breakup scan chains further into "reordering buckets". Reordering happens within these buckets only and the flops that are to be reordered are kept as floating in scanDEF.

Clock Re-convergence Pessimism Removal

C lock R e-convergence P essimism R emoval. Also called as CPPR . Let's consider a buffer that is placed in common path (both data path and clock path). Tool calculates max. delays for setup calculation and min. delays for hold (worst and best case analysis). When comes to OCV analysis, tool further considers, max. for data path and min. for clock path during setup analysis. max. for clock path and min. for data path during hold analysis. So, buffer placed in common path now has 2 values i.e., max. and min. values. As we know, a cell can't have two different values at a particular instant of time. Thereby we calculates the buffer value as, CRPR = Max. value - min. value While performing STA, for setup analysis, CRPR is added in RT whereas in hold analysis, it is subtracted from RT. RT + CRPR (for setup) RT - CRPR (for hold) Example regarding CRPR is shown above. For above figure, CRPR = 1ns ...

Power Dissipation

1. Static Power Dissipation - Due to leakage currents (without any operation) (standby mode) 2. Dynamic Power Dissipation - Due to switching (switching mode) Total power dissipation = Static power diss. + Dynamic power diss. Static power dissipation is due to: a) Gate oxide leakage currents b) Junction leakage currents c) Sub-threshold currents Dynamic power dissipation : a) switching p.d. b) short circuit p.d. c) glitching p.d. - large delays Power reduction techniques in CMOS 1. Reduce the supply voltage 2. Using variable clock frequencies and operating voltages. 3. First increase the performance of the circuit (by adding components in parallel) and then reduce the voltage of the circuit. *If voltage is reduced before increasing the performance, the delay of the circuit increases. 4. Clock gating and power gating. Dynamic power dissipation can be reduced by reducing: a) Clock frequency ...

STA Calculation

Setup analysis : AT <= RT Setup slack : RT - AT where AT = T L + T CK_Q + T COMBO RT = T - T S + T C Hold analysis : AT >= RT Hold slack : AT - RT where AT = T L + T CK_Q + T COMBO RT = T H + T C Here AT = Arrival Time RT = Required Time T L = Launch Time T C = Capture Time T S = Setup Time T H = Hold Time T = Time period (If the above conditions of the slack were not met, then they are said to be violated. It may cause timing failure of the design which in-turn causes damage of the chip.) *Tool goes for the worst case while analyzing setup slack and best case for hold slack analysis. Hence, it considers max. delay in data path for setup slack analysis and min. delay in data path for hold slack analysis. *If there is uncertainty(U), then tool considers RT - U for setup slack RT + U for hold slack because of worst and best case...

STA Basics

STA(Static Time Analysis) : It is the process of analysing the timing constraints of the design without any simulation/switching. Basically, Timing analysis is of 2 types. 1. STA - Static Timing Analysis 2. DTA - Dynamic Timing Analysis Setup time: min. amount of time for which the data signal is to be stable before the next active clock edge. Hold time: min. amount of time for which the data signal is to be stable after the first active clock edge. Launch flop : flop that is responsible for launching the data. Capture flop : flop that is responsible for capturing the data. Launch clock : clock responsible for making launch flop active. Capture clock : clock responsible for making capture flop active. Launch time : time taken for launching the data. Capture time : time taken for capturing the data. Data path : path of data signal (or) path starting from common point of clock network to th...