Physical Design is a process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them. It is the result of a synthesized netlist that has been placed and routed. The design flow deals with various steps involved such as follows: Synthesized netlist ⇓ Partitioning ⇓ Sanity checks ⇓ Floorplan ⇓ Power plan ⇓ Placement ⇓ Clock Tree Structure (CTS) ⇓ Routing ⇓ Signoff Sanity checks has to be performed before every stage in order to check whether our design is meeting the requirements for the next stage (or) whether its properly designed. Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That will be done by the front end engineers(RTL design team). The developed code is then compiled and as a result, a synthesized netlist is obtained. It contains the gate level model for the respective RTL code. .def is the output file at each s...
Formal Verification : It's also called as " Logic Equivalence Check ". It checks the functionality equivalence of the implementation design with reference design (golden design). It checks and verifies multiple rules which are configured for equivalence check and errors out if any mismatches are found between the designs. It ignores timing information. Formal verification is done before and after of, Logical Synthesis Physical Synthesis Place and Route It can be performed after every stage of PnR. Logical Synthesis : Reference : RTL file Implemented : Synthesized netlist / Gate level netlist Physical Synthesis : Reference : RTL file Implemented : Synthesized and modified netlist Place and Route : Reference : Synthesized netlist Implemented : Netlist extracted from optimized routed design S teps involved : Read Match Verify Debug Read : Reads and breaks both the designs into Logic cones and Compare points. (*...